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Message-ID: <20090921153801.GD30821@n2100.arm.linux.org.uk>
Date:	Mon, 21 Sep 2009 16:38:01 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	"Kirill A. Shutemov" <kirill@...temov.name>
Cc:	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Bityutskiy Artem <Artem.Bityutskiy@...ia.com>,
	Siarhei Siamashka <siarhei.siamashka@...ia.com>
Subject: Re: [PATCH v3 1/2] ARM: Introduce ARM_L1_CACHE_SHIFT to define
	cache line size

On Mon, Sep 21, 2009 at 02:19:57PM +0300, Kirill A. Shutemov wrote:
> On Mon, Sep 21, 2009 at 11:37 AM, Russell King - ARM Linux
> <linux@....linux.org.uk> wrote:
> > On Sat, Sep 12, 2009 at 11:48:30PM +0300, Kirill A. Shutemov wrote:
> >> Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
> >> It's not true at least for CPUs based on Cortex-A8.
> >
> > Please send this to the patch system.  There's no need to add the "V2"
> > comments to it when you do.
> >
> 
> #5716, #5717
> 
> BTW, I ,my pathes without change log in your git tree. Commits 910a17e
> and dca230f. What is wrong with it?

No need to resend them - sorry, I'd forgotten I'd merged them.
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