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Date:	Tue, 10 Nov 2009 19:09:39 GMT
From:	tip-bot for Dave Jones <davej@...hat.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
	davej@...hat.com, tglx@...utronix.de, mingo@...e.hu
Subject: [tip:x86/urgent] x86: Add new Intel CPU cache size descriptors

Commit-ID:  85160b92fbd35321104819283c91bfed2b553e3c
Gitweb:     http://git.kernel.org/tip/85160b92fbd35321104819283c91bfed2b553e3c
Author:     Dave Jones <davej@...hat.com>
AuthorDate: Tue, 10 Nov 2009 13:49:24 -0500
Committer:  Ingo Molnar <mingo@...e.hu>
CommitDate: Tue, 10 Nov 2009 20:06:16 +0100

x86: Add new Intel CPU cache size descriptors

The latest rev of Intel doc AP-485 details new cache descriptors
that we don't yet support. 12MB, 18MB and 24MB 24-way assoc L3
caches.

Signed-off-by: Dave Jones <davej@...hat.com>
LKML-Reference: <20091110184924.GA20337@...hat.com>
Signed-off-by: Ingo Molnar <mingo@...e.hu>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 804c40e..1410392 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -102,6 +102,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
 	{ 0xe2, LVL_3,    2048 },	/* 16-way set assoc, 64 byte line size */
 	{ 0xe3, LVL_3,    4096 },	/* 16-way set assoc, 64 byte line size */
 	{ 0xe4, LVL_3,    8192 },	/* 16-way set assoc, 64 byte line size */
+	{ 0xea, LVL_3,    12288 },	/* 24-way set assoc, 64 byte line size */
+	{ 0xeb, LVL_3,    18432 },	/* 24-way set assoc, 64 byte line size */
+	{ 0xec, LVL_3,    24576 },	/* 24-way set assoc, 64 byte line size */
 	{ 0x00, 0, 0}
 };
 
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