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Message-ID: <tip-e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149@git.kernel.org>
Date: Tue, 10 Nov 2009 20:55:08 GMT
From: tip-bot for Dave Jones <davej@...hat.com>
To: linux-tip-commits@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
davej@...hat.com, tglx@...utronix.de, mingo@...e.hu
Subject: [tip:x86/urgent] x86: Fix typo in Intel CPU cache size descriptor
Commit-ID: e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149
Gitweb: http://git.kernel.org/tip/e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149
Author: Dave Jones <davej@...hat.com>
AuthorDate: Tue, 10 Nov 2009 15:01:20 -0500
Committer: Ingo Molnar <mingo@...e.hu>
CommitDate: Tue, 10 Nov 2009 21:52:32 +0100
x86: Fix typo in Intel CPU cache size descriptor
I double-checked the datasheet. One of the existing
descriptors has a typo: it should be 2MB not 2038 KB.
Signed-off-by: Dave Jones <davej@...hat.com>
Cc: <stable@...nel.org> # .3x.x: 85160b9: x86: Add new Intel CPU cache size descriptors
Cc: <stable@...nel.org> # .3x.x
LKML-Reference: <20091110200120.GA27090@...hat.com>
Signed-off-by: Ingo Molnar <mingo@...e.hu>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 1410392..8178d03 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -94,7 +94,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
{ 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
{ 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
{ 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
- { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */
+ { 0xd7, LVL_3, 2048 }, /* 8-way set assoc, 64 byte line size */
{ 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
{ 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */
{ 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
--
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