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Date:	Fri, 13 Nov 2009 09:18:43 -0800
From:	"Luis R. Rodriguez" <mcgrof@...il.com>
To:	Corrado Zoccolo <czoccolo@...il.com>
Cc:	Arjan van de Ven <arjan@...ux.intel.com>,
	Senthil Balasubramanian <senthilkumar@...eros.com>,
	Aeolus Yang <Aeolus.Yang@...eros.com>,
	Jonathan May <Jonathan.May@...eros.com>,
	Thomas Renninger <trenn@...e.de>, davej@...hat.com,
	cpufreq@...r.kernel.org, linux-kernel@...r.kernel.org,
	Matthew Garrett <mjg@...hat.com>,
	Reinette Chatre <reinette.chatre@...el.com>,
	Amod Bodas <Amod.Bodas@...eros.com>,
	David Quan <David.Quan@...eros.com>,
	Kishore Jotwani <Kishore.Jotwani@...eros.com>,
	linux-wireless <linux-wireless@...r.kernel.org>
Subject: Re: [PATCH] cpu-freq: add troubleshooting section for FSB changes

On Tue, Nov 10, 2009 at 4:12 AM, Corrado Zoccolo <czoccolo@...il.com> wrote:
> Hi,
> On Mon, Nov 9, 2009 at 5:32 PM, Luis R. Rodriguez <mcgrof@...il.com> wrote:
>>
>> And we tested this (reducing the min cpu freq to one less than the
>> highest supported P state to avoid an FSB speed change) and it seems
>> doing the steps described here did not fix the issue. But at least now
>> if anyone else wants to verify this they can with some sort of
>> documentaiton.
>>
>> So to confirm though -- we are seeing a huge performance depredation
>> mainly on RX on an Intel Pine Trail platform with SpeedStep enabled on
>> the BIOS.
>>
>> Let me get into the specifics in case anyone is able to help. The
>> issue is with ath9k on RX and the CPU on C3 state requesting DMA over
>> PCI-E. We typically would get about 110 Mbps with an AR9285 (single
>> stream) but when SpeedStep is enabled it goes down to 25 Mbps. At the
>> PCI-E level we are seeing huge latencies introduced when SpeedStep is
>> used for DMA requests to the Intel root complex on the Intel Pine
>> trail platform. Latencies are about 20-60 us.
>
> You mentioned speedstep and cpufreq, but the problem is with C3 state
> and cpuidle (probably the BIOS mixes the two concepts, but we should
> keep them separated).
> C3 is not related to the core or FSB frequency, it is an idle state.
> When in C3, the CPU is not ready to perform any operation, not just
> slower, and depending on the CPU hw, it may take several us to wake up
> (even 85us, on an Atom).
>
>>
>> Is there a timeout threshold change that will cause the Intel chipset
>> wait for some time after completion before going into a C3 state? Are
>> there any other explanations for seeing such huge latencies on C3
>> state?
> There is a patch from Arjan for the cpuidle menu governor, that may fix it.
> http://linux.derkeiler.com/Mailing-Lists/Kernel/2009-09/msg05276.html
> It is already present in 2.6.32.

Thanks all for your feedback -- this was determined to be a BIOS bug
:) Anyway, hope you do consider the patch for inclusion.

  Luis
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