linux-kernel - Re: [RFC -tip] x86,io-apic: Do not map IO-APIC direct registers twice

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Message-ID: <20091113192242.GD5695@lenovo>
Date:	Fri, 13 Nov 2009 22:22:42 +0300
From:	Cyrill Gorcunov <gorcunov@...il.com>
To:	Yinghai Lu <yinghai@...nel.org>
Cc:	Ingo Molnar <mingo@...e.hu>,
	"Maciej W. Rozycki" <macro@...ux-mips.org>,
	x86team <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [RFC -tip] x86,io-apic: Do not map IO-APIC direct registers
	twice

On Fri, Nov 13, 2009 at 11:17:00AM -0800, Yinghai Lu wrote:
> >> Cyrill Gorcunov wrote:
> >>> On Thu, Nov 12, 2009 at 03:22:55PM -0800, Yinghai Lu wrote:
> >> 2. print out ...?
> > 
> > Print out what? Not sure I understand you right. Perhaps you mean
> > to check insert_resourse results?
...
> 
>   		apic_printk(APIC_VERBOSE,
>  			    "mapped IOAPIC to %08lx (%08lx)\n",
> -			    __fix_to_virt(idx), ioapic_phys);
> +			    __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
> 
> YH
> 

Updated version below, thanks Yinghai! Looks good?

	-- Cyrill
---
x86,io-apic: IO-APIC MMIO should not fail on resourse insertion

If IO-APIC base address is 1K aligned we should not fail
on resourse insertion procedure. For this sake we define
IO_APIC_SLOT_SIZE constant which should cover all IO-APIC
direct accessible registers.

An example of a such configuration is there

	http://marc.info/?l=linux-kernel&m=118114792006520

| Quoting the message
|
| IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
| IOAPIC[1]: apic_id 3, version 32, address 0xfec80000, GSI 24-47
| IOAPIC[2]: apic_id 4, version 32, address 0xfec80400, GSI 48-71
| IOAPIC[3]: apic_id 5, version 32, address 0xfec84000, GSI 72-95
| IOAPIC[4]: apic_id 8, version 32, address 0xfec84400, GSI 96-119

Reported-by: "Maciej W. Rozycki" <macro@...ux-mips.org>
CC: "Maciej W. Rozycki" <macro@...ux-mips.org>
CC: Yinghai Lu <yinghai@...nel.org>
Signed-off-by: Cyrill Gorcunov <gorcunov@...nvz.org>
---
 arch/x86/include/asm/apicdef.h |    7 +++++++
 arch/x86/kernel/apic/io_apic.c |   11 +++++------
 2 files changed, 12 insertions(+), 6 deletions(-)

Index: linux-2.6.git/arch/x86/include/asm/apicdef.h
=====================================================================
--- linux-2.6.git.orig/arch/x86/include/asm/apicdef.h
+++ linux-2.6.git/arch/x86/include/asm/apicdef.h
@@ -11,6 +11,13 @@
 #define IO_APIC_DEFAULT_PHYS_BASE	0xfec00000
 #define	APIC_DEFAULT_PHYS_BASE		0xfee00000
 
+/*
+ * We assume that it will be more then enough
+ * in feasible feauture to cover all direct
+ * accessible IO-APIC registers
+ */
+#define IO_APIC_SLOT_SIZE		1024
+
 #define	APIC_ID		0x20
 
 #define	APIC_LVR	0x30
Index: linux-2.6.git/arch/x86/kernel/apic/io_apic.c
=====================================================================
--- linux-2.6.git.orig/arch/x86/kernel/apic/io_apic.c
+++ linux-2.6.git/arch/x86/kernel/apic/io_apic.c
@@ -4133,18 +4133,17 @@ void __init ioapic_init_mappings(void)
 #ifdef CONFIG_X86_32
 fake_ioapic_page:
 #endif
-			ioapic_phys = (unsigned long)
-				alloc_bootmem_pages(PAGE_SIZE);
+			ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
 			ioapic_phys = __pa(ioapic_phys);
 		}
 		set_fixmap_nocache(idx, ioapic_phys);
-		apic_printk(APIC_VERBOSE,
-			    "mapped IOAPIC to %08lx (%08lx)\n",
-			    __fix_to_virt(idx), ioapic_phys);
+		apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
+			__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
+			ioapic_phys);
 		idx++;
 
 		ioapic_res->start = ioapic_phys;
-		ioapic_res->end = ioapic_phys + PAGE_SIZE-1;
+		ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
 		ioapic_res++;
 	}
 }
--
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