linux-kernel - Re: Perf events/ARM

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20091201143105.GB1183@elte.hu>
Date:	Tue, 1 Dec 2009 15:31:05 +0100
From:	Ingo Molnar <mingo@...e.hu>
To:	Jamie Iles <jamie@...ieiles.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>
Cc:	linux-kernel@...r.kernel.org
Subject: Re: Perf events/ARM


* Jamie Iles <jamie@...ieiles.com> wrote:

> Hi,
> 
> I'm looking at adding support for the hardware performance counters in ARMv6
> using the new perf events framework. I have a simple setup that uses the
> counters on their own, but wrt the perf events framework:
> 
> 	- what are the requirements of set_perf_event_pending() and
> 	perf_event_do_pending()? As far as I can tell from sparc/x86/powerpc,
> 	set_perf_event_pending() triggers an interrupt that then calls
> 	perf_event_do_pending(). Does perf_event_do_pending need to run in
> 	interrupt context or could I use a soft IRQ if platforms don't have a
> 	spare IRQ?

softirq would be fine too i suspect - but then you need to increase the 
buffering of perf_pending_head, as multiple hardirqs could hit before 
the softirq processing has finished.

As that gets complex quick, an acceptable first-order approach would be 
to just ignore those lost events and run it from a softirq - i _think_ 
everything should be OK.

> 	- ARM does not have proper support for atomic64's. Other than
> 	performance, would there be any known problems with using the generic
> 	spinlocked atomic64's?

Not a problem at all. Even performance-wise they are pretty nice - Paul 
has done a nice job hashing it along 16 spinlocks - so for small SMP 
systems there should be no global cacheline bounce.

	Ingo
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/