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Message-ID: <1266979689.23523.1669.camel@pasglop>
Date:	Wed, 24 Feb 2010 13:48:09 +1100
From:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
To:	Oliver Neukum <oliver@...kum.org>
Cc:	Catalin Marinas <catalin.marinas@....com>,
	Matthew Dharm <mdharm-kernel@...-eyed-alien.net>,
	Russell King - ARM Linux <linux@....linux.org.uk>,
	Greg KH <greg@...ah.com>,
	"Mankad, Maulik Ojas" <x0082077@...com>,
	Sergei Shtylyov <sshtylyov@...mvista.com>,
	Sebastian Siewior <bigeasy@...utronix.de>,
	linux-usb@...r.kernel.org,
	linux-kernel <linux-kernel@...r.kernel.org>,
	James Bottomley <James.Bottomley@...senpartnership.com>,
	"Shilimkar, Santosh" <santosh.shilimkar@...com>,
	Pavel Machek <pavel@....cz>, Ming Lei <tom.leiming@...il.com>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: USB mass storage and ARM cache coherency

On Fri, 2010-02-19 at 21:53 +0100, Oliver Neukum wrote:
> Am Freitag, 19. Februar 2010 18:36:51 schrieb Catalin Marinas:
> > If a page is already mapped in user space, flush_dcache_page() on ARM
> > does the flushing rather than deferring it to update_mmu_cache(). The
> > PIO HCD drivers, however, don't call flush_dcache_page(). Is it possible
> > that the HCD could transfer data into a page cache page already mapped
> > in user space? My understanding is that the scenario above is possible.
> 
> Yes, video drivers do that. 

In which case it would be up to the video driver to call
flush_dcache_page() (though if it's v4l you are talking about, maybe it
might make sense to push it into the v4l layer itself).

Cheers,
Ben.


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