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Message-ID: <87aattpi90.fsf@basil.nowhere.org>
Date: Sat, 27 Mar 2010 22:27:55 +0100
From: Andi Kleen <andi@...stfloor.org>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...e.hu>, LKML <linux-kernel@...r.kernel.org>,
Stephane Eranian <eranian@...gle.com>
Subject: Re: [PATCH] perf, x86: Add Nehelem PMU programming errata workaround
Peter Zijlstra <peterz@...radead.org> writes:
> Subject: perf, x86: Add Nehelem PMU programming errata workaround
> From: Peter Zijlstra <a.p.zijlstra@...llo.nl>
> Date: Fri Mar 26 13:59:41 CET 2010
>
> Implement the workaround for Intel Errata AAK100 and AAP53.
>
> Also, remove the Core-i7 name for Nehalem events since there are also
> Westmere based i7 chips.
Did you actually see this happen?
It looks like this will make the context switch into a perf
enabled process _MUCH_ more expensive, MSR writes are very slow.
-Andi
--
ak@...ux.intel.com -- Speaking for myself only.
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