linux-kernel - Re: [ath5k-devel] [PATCH v3] ath5k: disable ASPM

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Message-ID: <AANLkTinq-SxMHTrJM23WaeRMkU-2cySiVrkwCjDRS_o+@mail.gmail.com>
Date:	Mon, 26 Jul 2010 15:26:37 -0700
From:	"Luis R. Rodriguez" <mcgrof@...il.com>
To:	Matthew Garrett <mjg59@...f.ucam.org>
Cc:	Maxim Levitsky <maximlevitsky@...il.com>,
	"ath5k-devel@...ts.ath5k.org" <ath5k-devel@...ts.ath5k.org>,
	"linux-wireless@...r.kernel.org" <linux-wireless@...r.kernel.org>,
	David Quan <David.Quan@...eros.com>,
	"Luis R. Rodriguez" <mcgrof@...badil.infradead.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	"kernel-team@...ts.ubuntu.com" <kernel-team@...ts.ubuntu.com>,
	Luis Rodriguez <Luis.Rodriguez@...eros.com>,
	Jussi Kivilinna <jussi.kivilinna@...et.fi>,
	"tim.gardner@...onical.com" <tim.gardner@...onical.com>
Subject: Re: [ath5k-devel] [PATCH v3] ath5k: disable ASPM

On Mon, Jul 26, 2010 at 3:21 PM, Matthew Garrett <mjg59@...f.ucam.org> wrote:
> On Mon, Jul 26, 2010 at 03:15:32PM -0700, Luis R. Rodriguez wrote:
>> On Mon, Jul 26, 2010 at 2:25 PM, Matthew Garrett <mjg59@...f.ucam.org> wrote:
>> > This may need to be done on a chip by chip basis. Take a look at
>> > http://www.atheros.cz/inffile.php?inf=68&bit=32&atheros=AR5002G&system=4
>> > and some of the other inf files on that site to see which devices
>> > provide the PciASPMOptIn flag - those should support ASPM states even if
>> > they're pre-1.1 devices.
>>
>> I rather we not bother with these, lets simply follow the kernel's
>> lead here for its rule matching.
>
> Sorry? The idea is to indicate which chips support ASPM even though
> they're pre-PCIe 1.1. If all Atheros parts work fine with L1 then that
> makes things much easier, but it would be good to know the correct set
> of chips that are broken with L0s.

What I meant was that the PCI config space would already have L1
enabled if L1 worked, so I don't see why we would need to nitpick out
specifics here. All Atheros PCIE chips should work with L1. The advise
given is to disable L0s though. I believe AR2425 would be one which
likely had L0s enabled but requires it to be disabled. Not sure of
others. But this is why I am saying this can be done globally for all
ath5k chipsets.

  Luis
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