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Message-ID: <20100726222909.GA6773@srcf.ucam.org>
Date: Mon, 26 Jul 2010 23:29:09 +0100
From: Matthew Garrett <mjg59@...f.ucam.org>
To: "Luis R. Rodriguez" <mcgrof@...il.com>
Cc: Maxim Levitsky <maximlevitsky@...il.com>,
"ath5k-devel@...ts.ath5k.org" <ath5k-devel@...ts.ath5k.org>,
"linux-wireless@...r.kernel.org" <linux-wireless@...r.kernel.org>,
David Quan <David.Quan@...eros.com>,
"Luis R. Rodriguez" <mcgrof@...badil.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
"kernel-team@...ts.ubuntu.com" <kernel-team@...ts.ubuntu.com>,
Luis Rodriguez <Luis.Rodriguez@...eros.com>,
Jussi Kivilinna <jussi.kivilinna@...et.fi>,
"tim.gardner@...onical.com" <tim.gardner@...onical.com>
Subject: Re: [ath5k-devel] [PATCH v3] ath5k: disable ASPM
On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote:
> What I meant was that the PCI config space would already have L1
> enabled if L1 worked, so I don't see why we would need to nitpick out
> specifics here. All Atheros PCIE chips should work with L1. The advise
> given is to disable L0s though. I believe AR2425 would be one which
> likely had L0s enabled but requires it to be disabled. Not sure of
> others. But this is why I am saying this can be done globally for all
> ath5k chipsets.
If L1 is set but the chip is pre-PCIe 1.1 then we'll disable L1 unless
the driver tells us that it's functional. The .inf from the Windows
driver seemed to suggest that only a subset of the chips re-enabled L1
there, but if it's ok in general then that's a straightforward one-line
patch.
--
Matthew Garrett | mjg59@...f.ucam.org
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