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Message-ID: <alpine.BSF.2.00.1008030030430.1414@desktop>
Date:	Tue, 3 Aug 2010 00:36:35 -1000 (HST)
From:	Jeff Roberson <jroberson@...berson.net>
To:	linux-kernel@...r.kernel.org
cc:	aaronp@...strix.com
Subject: PCI-E Link training bug

Hello Folks,

At least one intel chipset will occasionally negotiate a 4x link for an 8x 
device in an 8x port.  It is a known errata in the 5400 mch.  Simply 
disabling and re-enabling the link is all that is required to restore full 
throughput.  Toggling the retrain bit in the pci-e link control register 
alone is insufficient.

I have added a small bit of code to the pcie port device which checks for 
this condition and attempts to retrain the link.  It is possible that it 
will give a false positive if the port is capable of accepting lesser 
width devices.  This should be harmless although I would not rule out poor 
implementations having issues with gratuitous retraining.

Thanks,
Jeff
View attachment "pcie.diff" of type "TEXT/PLAIN" (2427 bytes)

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