lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <60320.1280838641@localhost>
Date:	Tue, 03 Aug 2010 08:30:41 -0400
From:	Valdis.Kletnieks@...edu
To:	Jeff Roberson <jroberson@...berson.net>
Cc:	linux-kernel@...r.kernel.org, aaronp@...strix.com
Subject: Re: PCI-E Link training bug

On Tue, 03 Aug 2010 00:36:35 -1000, Jeff Roberson said:

> At least one intel chipset will occasionally negotiate a 4x link for an 8x 
> device in an 8x port.  It is a known errata in the 5400 mch.  

Can this get wrapped in some sort of 'if (chipset == MCH5400)'?  There's no
sense in adding an entire second of delay going around this loop 4 times when
it's a valid config on a non-5400 chipset.


Content of type "application/pgp-signature" skipped

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ