linux-kernel - Re: PCI-E Link training bug

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20100803085239.6766fb0e@virtuousgeek.org>
Date:	Tue, 3 Aug 2010 08:52:39 -0700
From:	Jesse Barnes <jbarnes@...tuousgeek.org>
To:	Valdis.Kletnieks@...edu
Cc:	Jeff Roberson <jroberson@...berson.net>,
	linux-kernel@...r.kernel.org, aaronp@...strix.com
Subject: Re: PCI-E Link training bug

On Tue, 03 Aug 2010 08:30:41 -0400
Valdis.Kletnieks@...edu wrote:

> On Tue, 03 Aug 2010 00:36:35 -1000, Jeff Roberson said:
> 
> > At least one intel chipset will occasionally negotiate a 4x link for an 8x 
> > device in an 8x port.  It is a known errata in the 5400 mch.  
> 
> Can this get wrapped in some sort of 'if (chipset == MCH5400)'?  There's no
> sense in adding an entire second of delay going around this loop 4 times when
> it's a valid config on a non-5400 chipset.

Yeah, it would be good to limit it to affected chipsets.  Also, please
post it to linux-pci@...r.kernel.org as well, and cc me, and we'll get
the fix in quickly.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/