linux-kernel - Re: Attempted summary of suspend-blockers LKML thread, take three

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Date:	Sat, 14 Aug 2010 08:10:48 -0700
From:	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To:	Pavel Machek <pavel@....cz>
Cc:	Alan Cox <alan@...rguk.ukuu.org.uk>,
	Felipe Contreras <felipe.contreras@...il.com>,
	"Ted Ts'o" <tytso@....edu>, david@...g.hm,
	Brian Swetland <swetland@...gle.com>,
	linux-pm@...ts.linux-foundation.org, linux-kernel@...r.kernel.org,
	arve@...roid.com, mjg59@...f.ucam.org, florian@...kler.org,
	rjw@...k.pl, stern@...land.harvard.edu, peterz@...radead.org,
	tglx@...utronix.de, menage@...gle.com, david-b@...bell.net,
	James.Bottomley@...e.de, arjan@...radead.org, swmike@....pp.se,
	galibert@...ox.com, dipankar@...ibm.com
Subject: Re: Attempted summary of suspend-blockers LKML thread, take three

On Sat, Aug 14, 2010 at 09:38:44AM +0200, Pavel Machek wrote:
> Hi!
> 
> > > > > Think in terms of an ARM laptop. What good is opportunistic suspend if
> > > > > it's not going to help when the laptop is being used?
> > > > 
> > > > For when the laptop is not being used, presumably.
> > > 
> > > Or in time between keystrokes for most of the platform (backlight
> > > excepted). The Intel MID x86 devices are at the point that suspend/resume
> > > time on x86 is being hurt by the kernel rewriting smp alternatives as we
> > > go from 2 processors live to 1 and back.
> > 
> > Given that you are talking about going from 2 processors to 1 and back,
> > I would guess that you are not actually talking about suspend/resume,
> > which is a system-wide thing rather than a CPU-by-CPU thing.  I am not
> > sure whether you are using CPU hotplug or invoking SMP alternatives once
> > all but one CPU is idle.
> 
> When entering system suspend, we disable non-boot-CPUs to simplify
> locking. We reenable them when going out of suspend.

Thank you for the info, Pavel!

So once you are down to one CPU, the last CPU shuts the system off,
itself included?  Or does the last CPU "run" in a deep idle state
throughout suspend?  (My guess is the former, and I am also curious
whether the cache SRAMs are powered off, etc.  But figured I should ask
rather than guessing.)

							Thanx, Paul
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