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Message-ID: <4C692B42.9050407@neli.hopto.org>
Date: Mon, 16 Aug 2010 14:12:50 +0200
From: Micha Nelissen <micha@...i.hopto.org>
To: Alexandre Bounine <alexandre.bounine@....com>
CC: akpm@...ux-foundation.org, linux-kernel@...r.kernel.org,
linuxppc-dev@...abs.org
Subject: Re: [PATCH 2/9] RapidIO, powerpc/85xx: modify RIO port-write interrupt
handler
Alexandre Bounine wrote:
> - Rearranged RIO port-write interrupt handling to perform message buffering
> as soon as possible.
I don't understand this comment: you still schedule work to read the
port-write queue; so how is this message buffering performed as soon as
possible?
> - Modified to disable port-write controller when clearing Transaction Error (TE)
> bit.
> /* Schedule deferred processing if PW was received */
> - if (ipwsr & RIO_IPWSR_QFI) {
> + if ((ipwmr & RIO_IPWMR_QFIE) && (ipwsr & RIO_IPWSR_QFI)) {
Why check the QFIE bit also?
> +pw_done:
> + if (epwisr & 0x80000000) {
Magic value.
Micha
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