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Message-ID: <4CC1E717.7070707@ti.com>
Date: Fri, 22 Oct 2010 15:33:43 -0400
From: Cyril Chemparathy <cyril@...com>
To: Arnd Bergmann <arnd@...db.de>
CC: Andrew Morton <akpm@...ux-foundation.org>,
"davinci-linux-open-source@...ux.davincidsp.com"
<davinci-linux-open-source@...ux.davincidsp.com>,
"spi-devel-general@...ts.sourceforge.net"
<spi-devel-general@...ts.sourceforge.net>,
"broonie@...nsource.wolfsonmicro.com"
<broonie@...nsource.wolfsonmicro.com>,
"lrg@...mlogic.co.uk" <lrg@...mlogic.co.uk>,
"dbrownell@...rs.sourceforge.net" <dbrownell@...rs.sourceforge.net>,
"grant.likely@...retlab.ca" <grant.likely@...retlab.ca>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"rpurdie@...ys.net" <rpurdie@...ys.net>
Subject: Re: [PATCH v3 01/12] misc: add driver for sequencer serial port
On 10/22/2010 08:48 AM, Arnd Bergmann wrote:
> On Friday 22 October 2010 14:39:33 Cyril Chemparathy wrote:
>>>> +/* Register Access Helpers */
>>>> +static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
>>>> +{
>>>> + return __raw_readl(ssp->regs + reg);
>>>> +}
>>>> +
>>>> +static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
>>>> +{
>>>> + __raw_writel(val, ssp->regs + reg);
>>>> +}
>>>
>>> Why are the __raw functions used here?
>>>
>>
>> These registers are to be accessed native endian at all times, and
>> therefore the le32 conversion done otherwise is inappropriate.
>
> Won't that break on out-of-order CPUs that need the extra synchronization
> done in readl/writel?
>
AFAICS, ioremap()ed space on ARMv6 should be strongly ordered.
>
> ...
>
Thanks
Cyril.
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