linux-kernel - Re: [PATCH v3 01/12] misc: add driver for sequencer serial port

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Message-ID: <20101022224612.GA6079@n2100.arm.linux.org.uk>
Date:	Fri, 22 Oct 2010 23:46:12 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Cyril Chemparathy <cyril@...com>
Cc:	Arnd Bergmann <arnd@...db.de>,
	"davinci-linux-open-source@...ux.davincidsp.com" 
	<davinci-linux-open-source@...ux.davincidsp.com>,
	"dbrownell@...rs.sourceforge.net" <dbrownell@...rs.sourceforge.net>,
	"broonie@...nsource.wolfsonmicro.com" 
	<broonie@...nsource.wolfsonmicro.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"grant.likely@...retlab.ca" <grant.likely@...retlab.ca>,
	"rpurdie@...ys.net" <rpurdie@...ys.net>,
	"spi-devel-general@...ts.sourceforge.net" 
	<spi-devel-general@...ts.sourceforge.net>,
	Andrew Morton <akpm@...ux-foundation.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"lrg@...mlogic.co.uk" <lrg@...mlogic.co.uk>
Subject: Re: [PATCH v3 01/12] misc: add driver for sequencer serial port

On Fri, Oct 22, 2010 at 03:33:43PM -0400, Cyril Chemparathy wrote:
> On 10/22/2010 08:48 AM, Arnd Bergmann wrote:
> > On Friday 22 October 2010 14:39:33 Cyril Chemparathy wrote:
> >>>> +/* Register Access Helpers */
> >>>> +static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
> >>>> +{
> >>>> +    return __raw_readl(ssp->regs + reg);
> >>>> +}
> >>>> +
> >>>> +static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
> >>>> +{
> >>>> +    __raw_writel(val, ssp->regs + reg);
> >>>> +}
> >>>
> >>> Why are the __raw functions used here?
> >>>
> >>
> >> These registers are to be accessed native endian at all times, and
> >> therefore the le32 conversion done otherwise is inappropriate.
> > 
> > Won't that break on out-of-order CPUs that need the extra synchronization
> > done in readl/writel?
> > 
> 
> AFAICS, ioremap()ed space on ARMv6 should be strongly ordered.

No.  ioremap'd space is device memory on ARMv6 and above, which means
if you care about the ordering of writes to device vs memory, you
need barriers.

Nevertheless, individual reads/writes to devices will be in program
order, but writes may be delayed.
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