linux-kernel - Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE

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Message-ID: <AANLkTimdp1teeaZkn2h32TQjaWxqegp27TNq+rvQcxAF@mail.gmail.com>
Date:	Tue, 2 Nov 2010 02:55:46 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	Robert Schöne <robert.schoene@...dresden.de>
Cc:	Vince Weaver <vweaver1@...s.utk.edu>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Robert Richter <robert.richter@....com>,
	Ingo Molnar <mingo@...e.hu>, x86 <x86@...nel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and
 PERF_COUNT_HW_CACHE_MISSES for AMD

Hi,



On Mon, Nov 1, 2010 at 3:11 PM, Robert Schöne
<robert.schoene@...dresden.de> wrote:
>
> The current arch/x86/kernel/cpu/perf_event_amd.c file lists
> L1-Instruction-Cache Misses and Accesses as PERF_COUNT_HW_CACHE_MISSES
> resp. PERF_COUNT_HW_CACHE_REFERENCES.
>
I always thought PERF_COUNT_HW_CACHE_* was about data cache misses.
But given that there is no clear definitions for those events, it
creates confusion.

If you change the meaning of HW_CACHE_MISSES, then seems to me, you need
to change the mapping in the perf tool, because now it includes both data+code.


> This fix uses L2C-Misses and Accesses instead. (Real LLC-events would be
> better, but there are some restrictions for Northbridge Events on AMD).
>
And those constraints are handled correctly by the kernel.

The constraint is such that you cannot have more than 4 instances of
Northbridge events active at the same time per core. If you do, then one
of them will starve (if issued from different cores).


> --- a/arch/x86/kernel/cpu/perf_event_amd.c
> +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> @@ -100,8 +100,8 @@ static const u64 amd_perfmon_event_map[] =
>  {
>   [PERF_COUNT_HW_CPU_CYCLES]           = 0x0076,
>   [PERF_COUNT_HW_INSTRUCTIONS]         = 0x00c0,
> -  [PERF_COUNT_HW_CACHE_REFERENCES]     = 0x0080,
> -  [PERF_COUNT_HW_CACHE_MISSES]         = 0x0081,
> +  [PERF_COUNT_HW_CACHE_REFERENCES]     = 0x037D,
> +  [PERF_COUNT_HW_CACHE_MISSES]         = 0x037E,
>   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]  = 0x00c2,
>   [PERF_COUNT_HW_BRANCH_MISSES]                = 0x00c3,
>  };
>
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