linux-kernel - [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE

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Message-ID: <1288620663.2712.84.camel@localhost>
Date:	Mon, 01 Nov 2010 15:11:03 +0100
From:	Robert Schöne <robert.schoene@...dresden.de>
To:	Stephane Eranian <eranian@...gle.com>,
	Vince Weaver <vweaver1@...s.utk.edu>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Robert Richter <robert.richter@....com>,
	Ingo Molnar <mingo@...e.hu>
Cc:	x86 <x86@...nel.org>, linux-kernel <linux-kernel@...r.kernel.org>
Subject: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and
 PERF_COUNT_HW_CACHE_MISSES for AMD

The current arch/x86/kernel/cpu/perf_event_amd.c file lists
L1-Instruction-Cache Misses and Accesses as PERF_COUNT_HW_CACHE_MISSES
resp. PERF_COUNT_HW_CACHE_REFERENCES.

This fix uses L2C-Misses and Accesses instead. (Real LLC-events would be
better, but there are some restrictions for Northbridge Events on AMD).

The event codes are copied from the list of cache events from the same
file.


Signed-off-by: Robert Schoene <robert.schoene@...dresden.de>


--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -100,8 +100,8 @@ static const u64 amd_perfmon_event_map[] =
 {
   [PERF_COUNT_HW_CPU_CYCLES]           = 0x0076,
   [PERF_COUNT_HW_INSTRUCTIONS]         = 0x00c0,
-  [PERF_COUNT_HW_CACHE_REFERENCES]     = 0x0080,
-  [PERF_COUNT_HW_CACHE_MISSES]         = 0x0081,
+  [PERF_COUNT_HW_CACHE_REFERENCES]     = 0x037D,
+  [PERF_COUNT_HW_CACHE_MISSES]         = 0x037E,
   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]  = 0x00c2,
   [PERF_COUNT_HW_BRANCH_MISSES]                = 0x00c3,
 };

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