| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <1289765858.24270.240.camel@m0nster> Date: Sun, 14 Nov 2010 12:17:38 -0800 From: Daniel Walker <dwalker@...eaurora.org> To: Stepan Moskovchenko <stepanm@...eaurora.org> Cc: davidb@...eaurora.org, bryanh@...eaurora.org, linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 09/14] msm: iommu: Kconfig option for cacheable page tables On Fri, 2010-11-12 at 19:29 -0800, Stepan Moskovchenko wrote: > > +config IOMMU_PGTABLES_L2 > + depends on ARCH_MSM8X60 > + depends on MMU > + depends on CPU_DCACHE_DISABLE=n > + depends on SMP > + bool "Cacheable IOMMU page tables" > + default y > + help > + Allows the IOMMU page tables to be brought into the L2 cache. This > + improves the TLB miss latency at the expense of potential pollution > + of the L2 cache. This option has been shown to improve multimedia > + performance in some cases. > + > + If unsure, say Y here. Why would someone want this off? The other thing is that you usually want this included with the code that uses the option. Daniel -- Sent by an consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists