linux-kernel - Re: [RFC PATCH 2/3 v2] perf: Implement Nehalem uncore pmu

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Message-ID: <AANLkTikt8AkZjNahrzTStJ5qM0D4Z+H_7snZBgsABm24@mail.gmail.com>
Date:	Tue, 23 Nov 2010 11:17:09 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	Lin Ming <ming.m.lin@...el.com>
Cc:	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Ingo Molnar <mingo@...e.hu>, Andi Kleen <andi@...stfloor.org>,
	lkml <linux-kernel@...r.kernel.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Arjan van de Ven <arjan@...radead.org>
Subject: Re: [RFC PATCH 2/3 v2] perf: Implement Nehalem uncore pmu

Lin,

On Sun, Nov 21, 2010 at 1:01 PM, Lin Ming <ming.m.lin@...el.com> wrote:
> +static void uncore_pmu_enable_all(void)
> +{
> +       u64 ctrl;
> +
> +       /*
> +        * (0xFULL << 48): 1 of the 4 cores can receive NMI each time
> +        * but we don't know which core will receive the NMI when overflow happens
> +        */

That does not sound right. If you set bit 48-51 to 1, then all 4 cores
will receive EVERY
interrupt, i.e., it's a broadcast. That seems to contradict your
comment: 1 of the 4. Unless
you meant, they all get the interrupt and one will handle it, the
other will find nothing to
process. But I don't see the atomic op that would make this true in
uncore_handle_irq().

I also think that if you want all processors to receive the
interrupts, then the mask should
be 0xff when HT is on. The manual is rather obscure on this, but it
does make sense.


> +       ctrl = ((1 << UNCORE_NUM_GENERAL_COUNTERS) - 1) | (0xFULL << 48);
> +       ctrl |= MSR_UNCORE_PERF_GLOBAL_CTRL_EN_FC0;
> +
> +       /*
> +        * Freeze the uncore pmu on overflow of any uncore counter.
> +        * This makes unocre NMI handling easier.
> +        */
> +       ctrl |= MSR_UNCORE_PERF_GLOBAL_CTRL_PMI_FRZ;
> +
> +       wrmsrl(MSR_UNCORE_PERF_GLOBAL_CTRL, ctrl);
> +}
> +
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