linux-kernel - [PATCH] [49/223] drm/i915: diasable clock gating for the panel power sequencer

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Date:	Mon, 13 Dec 2010 00:45:46 +0100 (CET)
From:	Andi Kleen <andi@...stfloor.org>
To:	jbarnes@...tuousgeek.org, chris@...is-wilson.co.uk, gregkh@...e.de,
	ak@...ux.intel.com, linux-kernel@...r.kernel.org, stable@...nel.org
Subject: [PATCH] [49/223] drm/i915: diasable clock gating for the panel power sequencer

2.6.35-longterm review patch.  If anyone has any objections, please let me know.

------------------
From: Jesse Barnes <jbarnes@...tuousgeek.org>

commit 382b09362711d7d03272230a33767015a277926e upstream.

Needed on Ibex Peak and Cougar Point or the panel won't always come on.

Signed-off-by: Jesse Barnes <jbarnes@...tuousgeek.org>
Signed-off-by: Chris Wilson <chris@...is-wilson.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@...e.de>
Signed-off-by: Andi Kleen <ak@...ux.intel.com>

---
 drivers/gpu/drm/i915/i915_reg.h      |    3 +++
 drivers/gpu/drm/i915/intel_display.c |    7 +++++++
 2 files changed, 10 insertions(+)

Index: linux/drivers/gpu/drm/i915/i915_reg.h
===================================================================
--- linux.orig/drivers/gpu/drm/i915/i915_reg.h
+++ linux/drivers/gpu/drm/i915/i915_reg.h
@@ -2709,6 +2709,9 @@
 #define FDI_RXB_CHICKEN         0xc2010
 #define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)
 
+#define SOUTH_DSPCLK_GATE_D	0xc2020
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+
 /* CPU: FDI_TX */
 #define FDI_TXA_CTL             0x60100
 #define FDI_TXB_CTL             0x61100
Index: linux/drivers/gpu/drm/i915/intel_display.c
===================================================================
--- linux.orig/drivers/gpu/drm/i915/intel_display.c
+++ linux/drivers/gpu/drm/i915/intel_display.c
@@ -5416,6 +5416,13 @@ void intel_init_clock_gating(struct drm_
 		I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 
 		/*
+		 * On Ibex Peak and Cougar Point, we need to disable clock
+		 * gating for the panel power sequencer or it will fail to
+		 * start up when no ports are active.
+		 */
+		I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+
+		/*
 		 * According to the spec the following bits should be set in
 		 * order to enable memory self-refresh
 		 * The bit 22/21 of 0x42004
--
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