linux-kernel - [PATCH] [45/223] drm/radeon/kms: properly compute group

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Date:	Mon, 13 Dec 2010 00:45:42 +0100 (CET)
From:	Andi Kleen <andi@...stfloor.org>
To:	alexdeucher@...il.com, airlied@...hat.com, gregkh@...e.de,
	ak@...ux.intel.com, linux-kernel@...r.kernel.org, stable@...nel.org
Subject: [PATCH] [45/223] drm/radeon/kms: properly compute group_size on 6xx/7xx

2.6.35-longterm review patch.  If anyone has any objections, please let me know.

------------------
From: Alex Deucher <alexdeucher@...il.com>

commit 881fe6c1d06bf49f4ab7aef212cdaf66bd059614 upstream.

Needed for tiled surfaces.

Signed-off-by: Alex Deucher <alexdeucher@...il.com>
Signed-off-by: Dave Airlie <airlied@...hat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...e.de>
Signed-off-by: Andi Kleen <ak@...ux.intel.com>

---
 drivers/gpu/drm/radeon/r600.c  |    7 +++++--
 drivers/gpu/drm/radeon/rv770.c |    9 +++++----
 2 files changed, 10 insertions(+), 6 deletions(-)

Index: linux/drivers/gpu/drm/radeon/r600.c
===================================================================
--- linux.orig/drivers/gpu/drm/radeon/r600.c
+++ linux/drivers/gpu/drm/radeon/r600.c
@@ -1592,8 +1592,11 @@ void r600_gpu_init(struct radeon_device
 	rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
 	rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 	tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
-	tiling_config |= GROUP_SIZE(0);
-	rdev->config.r600.tiling_group_size = 256;
+	tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
+	if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
+		rdev->config.r600.tiling_group_size = 512;
+	else
+		rdev->config.r600.tiling_group_size = 256;
 	tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 	if (tmp > 3) {
 		tiling_config |= ROW_TILING(3);
Index: linux/drivers/gpu/drm/radeon/rv770.c
===================================================================
--- linux.orig/drivers/gpu/drm/radeon/rv770.c
+++ linux/drivers/gpu/drm/radeon/rv770.c
@@ -627,10 +627,11 @@ static void rv770_gpu_init(struct radeon
 	else
 		gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 	rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
-
-	gb_tiling_config |= GROUP_SIZE(0);
-	rdev->config.rv770.tiling_group_size = 256;
-
+	gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
+	if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
+		rdev->config.rv770.tiling_group_size = 512;
+	else
+		rdev->config.rv770.tiling_group_size = 256;
 	if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 		gb_tiling_config |= ROW_TILING(3);
 		gb_tiling_config |= SAMPLE_SPLIT(3);
--
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