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Date: Mon, 20 Dec 2010 18:13:43 +0100 From: Hans Rosenfeld <hans.rosenfeld@....com> To: <hpa@...or.com>, <tglx@...utronix.de>, <mingo@...e.hu> CC: <linux-kernel@...r.kernel.org>, <andreas.herrmann3@....com>, Hans Rosenfeld <hans.rosenfeld@....com> Subject: [PATCH 0/4] x86, amd: family 0x15 L3 cache features This patch set applies to tip/x86/amd-nb f658bcfb. It enables L3 cache index disable and adds support for L3 cache partitioning on family 0x15 CPUs. Andreas Herrmann (1): x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld (3): x86, amd: Enable L3 cache index disable on family 0x15 x86, amd: Extend AMD northbridge caching code to support "Link Control" devices x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs arch/x86/include/asm/amd_nb.h | 4 ++ arch/x86/kernel/amd_nb.c | 69 ++++++++++++++++++++++++++++++- arch/x86/kernel/cpu/amd.c | 8 +++- arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++----- arch/x86/kernel/smpboot.c | 1 + include/linux/pci_ids.h | 1 + 6 files changed, 140 insertions(+), 16 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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