linux-kernel - Re: [PATCH RESEND percpu#for-next] percpu: align percpu readmostly subsection to cacheline

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4D18FF39.6080101@zytor.com>
Date:	Mon, 27 Dec 2010 13:03:53 -0800
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Sam Ravnborg <sam@...nborg.org>
CC:	Tejun Heo <tj@...nel.org>, Shaohua Li <shaohua.li@...el.com>,
	lkml <linux-kernel@...r.kernel.org>,
	Andrew Morton <akpm@...ux-foundation.org>,
	eric.dumazet@...il.com, linux-arch@...r.kernel.org
Subject: Re: [PATCH RESEND percpu#for-next] percpu: align percpu readmostly
 subsection to cacheline

On 12/27/2010 12:43 PM, Sam Ravnborg wrote:
> 
> It would have been better to include cache.h and then use L1_CACHE_BYTES,
> as the value differs for EV4.
> It will work with 64 as this is the bigger of the two.
> 
> It looks like we could do this for almost all archs.
> But then I am not sure if "L1_CACHE_BYTES" is the same as
> a cacheline on the different archs.
> 

For x86, L1 is definitely not the right cache line to use, in terms of
what matters for SMP sharing.  And yes, there are x86's with smaller L1
than L2/3 cache line size.

	-hpa

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/