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Message-ID: <AANLkTims=DvdmDPET=G-_9w7Za2O_kkQhgQF8fKMV_x1@mail.gmail.com>
Date: Mon, 28 Feb 2011 13:25:46 +0100
From: Stephane Eranian <eranian@...gle.com>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Lin Ming <ming.m.lin@...el.com>, Ingo Molnar <mingo@...e.hu>,
Andi Kleen <andi@...stfloor.org>,
lkml <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 -tip] perf: x86, add SandyBridge support
On Mon, Feb 28, 2011 at 10:15 AM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
> On Mon, 2011-02-28 at 15:22 +0800, Lin Ming wrote:
>> This patch adds basic SandyBridge support, including hardware cache
>> events and PEBS events support.
>>
>> LLC-* hareware cache events don't work for now, it depends on the
>> offcore patches.
>
> What's the status of those, Stephane reported some problems last I
> remember?
>
>
>> #define INTEL_EVENT_CONSTRAINT(c, n) \
>> EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
>> +#define INTEL_EVENT_CONSTRAINT2(c, n) \
>> + EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
>
> That's a particularly bad name, how about something like
>
> INTEL_UEVENT_CONSTRAINT or somesuch.
>
>> @@ -702,7 +738,13 @@ static void intel_ds_init(void)
>> printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
>> x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
>> x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
>> - x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
>> + switch (boot_cpu_data.x86_model) {
>> + case 42: /* SandyBridge */
>> + x86_pmu.pebs_constraints = intel_snb_pebs_events;
>> + break;
>> + default:
>> + x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
>> + }
>> break;
>>
>> default:
>
> We already have this massive model switch right after this function,
> might as well move the pebs constraint assignment there.
>
My PEBS patch was going to cleanup this part, though it was using
it's own switch
statement.
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