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Date: Mon, 28 Feb 2011 22:02:11 +0800 From: Lin Ming <ming.m.lin@...el.com> To: Ingo Molnar <mingo@...e.hu> Cc: Stephane Eranian <eranian@...gle.com>, Peter Zijlstra <a.p.zijlstra@...llo.nl>, Andi Kleen <andi@...stfloor.org>, lkml <linux-kernel@...r.kernel.org> Subject: Re: [PATCH v2 -tip] perf: x86, add SandyBridge support On Mon, 2011-02-28 at 17:08 +0800, Ingo Molnar wrote: > * Lin Ming <ming.m.lin@...el.com> wrote: > > > > In other words, bit 0-3 of the umask cannot be zero. > > > > I got the umask from "Table 30-20. PEBS Performance Events for Intel > > microarchitecture code name Sandy Bridge". > > > > But from "Table A-2. Non-Architectural Performance Events In the Processor Core > > for Intel Core Processor 2xxx Series", the combinations are needed as you show > > above. > > > > Which one is correct? > > Since you have access to the hardware, could you please test and see it in practice > which one is correct? Stephane is right, need the combination. Sorry that I may made mistake when I tested 0xd0 pebs events. Re-test all PEBS events, now only below 2 events need more support to work. PEBS_EVENT_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ PEBS_EVENT_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORE*/ > > Thanks, > > Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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