linux-kernel - [tip:perf/urgent] perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus

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Message-ID: <tip-83112e688f5f05dea1e63787db9a6c16b2887a1d@git.kernel.org>
Date:	Tue, 19 Apr 2011 12:03:56 GMT
From:	tip-bot for Andre Przywara <andre.przywara@....com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...hat.com,
	robert.richter@....com, a.p.zijlstra@...llo.nl,
	andre.przywara@....com, tglx@...utronix.de, mingo@...e.hu
Subject: [tip:perf/urgent] perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus

Commit-ID:  83112e688f5f05dea1e63787db9a6c16b2887a1d
Gitweb:     http://git.kernel.org/tip/83112e688f5f05dea1e63787db9a6c16b2887a1d
Author:     Andre Przywara <andre.przywara@....com>
AuthorDate: Sat, 16 Apr 2011 02:27:53 +0200
Committer:  Ingo Molnar <mingo@...e.hu>
CommitDate: Tue, 19 Apr 2011 10:07:54 +0200

perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus

With AMD cpu family 15h a unit mask was introduced for the Data Cache
Miss event (0x041/L1-dcache-load-misses). We need to enable bit 0
(first data cache miss or streaming store to a 64 B cache line) of
this mask to proper count data cache misses.

Now we set this bit for all families and models. In case a PMU does
not implement a unit mask for event 0x041 the bit is ignored.

Signed-off-by: Andre Przywara <andre.przywara@....com>
Signed-off-by: Robert Richter <robert.richter@....com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Link: http://lkml.kernel.org/r/1302913676-14352-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@...e.hu>
---
 arch/x86/kernel/cpu/perf_event_amd.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 461f62b..4e16138 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -8,7 +8,7 @@ static __initconst const u64 amd_hw_cache_event_ids
  [ C(L1D) ] = {
 	[ C(OP_READ) ] = {
 		[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
-		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
+		[ C(RESULT_MISS)   ] = 0x0141, /* Data Cache Misses          */
 	},
 	[ C(OP_WRITE) ] = {
 		[ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
--
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