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Message-ID: <20110422195720.GB17583@elte.hu>
Date:	Fri, 22 Apr 2011 21:57:20 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Andi Kleen <ak@...ux.intel.com>
Cc:	Stephane Eranian <eranian@...gle.com>,
	Arnaldo Carvalho de Melo <acme@...radead.org>,
	linux-kernel@...r.kernel.org,
	Peter Zijlstra <peterz@...radead.org>,
	Lin Ming <ming.m.lin@...el.com>,
	Arnaldo Carvalho de Melo <acme@...hat.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>, eranian@...il.com,
	Arun Sharma <asharma@...com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [generalized cache events] Re: [PATCH 1/1] perf tools: Add
 missing user space support for config1/config2


* Andi Kleen <ak@...ux.intel.com> wrote:

> > Once you have clear and precise definition, then we can look at the actual
> > events and figure out a mapping.
> 
> It's unclear this can be even done. Linux runs on a wide variety of micro
> architectures, with all kinds of cache architectures.
> 
> Micro architectures are so different. I suspect a "generic" definition would
> need to be so vague as to be useless.

Not really. I gave a very specific example which solved a common and real 
problem, using L1-loads and L1-load-misses events.

> This in general seems to be the problem of the current cache events.
> 
> Overall for any interesting analysis you need to go CPU specific. Abstracted 
> performance analysis is a contradiction in terms.

Nothing of what i did in that example was CPU or microarchitecture specific.

Really, you are making this more complex than it really is. Just check the 
cache profiling example i gave, it works just fine today.

Thanks,

	Ingo
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