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Message-ID: <20110422203222.GA21219@elte.hu>
Date: Fri, 22 Apr 2011 22:32:22 +0200
From: Ingo Molnar <mingo@...e.hu>
To: arun@...rma-home.net
Cc: Stephane Eranian <eranian@...gle.com>,
Arnaldo Carvalho de Melo <acme@...radead.org>,
linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>,
Peter Zijlstra <peterz@...radead.org>,
Lin Ming <ming.m.lin@...el.com>,
Arnaldo Carvalho de Melo <acme@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <a.p.zijlstra@...llo.nl>, eranian@...il.com,
Arun Sharma <asharma@...com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [generalized cache events] Re: [PATCH 1/1] perf tools: Add
missing user space support for config1/config2
* Ingo Molnar <mingo@...e.hu> wrote:
> * arun@...rma-home.net <arun@...rma-home.net> wrote:
>
> > On Fri, Apr 22, 2011 at 12:52:11PM +0200, Ingo Molnar wrote:
> > >
> > > Using the generalized cache events i can run:
> > >
> > > $ perf stat --repeat 10 -e cycles:u -e instructions:u -e l1-dcache-loads:u -e l1-dcache-load-misses:u ./array
> > >
> > > Performance counter stats for './array' (10 runs):
> > >
> > > 6,719,130 cycles:u ( +- 0.662% )
> > > 5,084,792 instructions:u # 0.757 IPC ( +- 0.000% )
> > > 1,037,032 l1-dcache-loads:u ( +- 0.009% )
> > > 1,003,604 l1-dcache-load-misses:u ( +- 0.003% )
> > >
> > > 0.003802098 seconds time elapsed ( +- 13.395% )
> > >
> > > I consider that this is 'bad', because for almost every dcache-load there's a
> > > dcache-miss - a 99% L1 cache miss rate!
> >
> > One could argue that all you need is cycles and instructions. [...]
>
> Yes, and note that with instructions events we even have skid-less PEBS
> profiling so seeing the precise .
- location of instructions is possible.
[ An email gremlin ate that part of the sentence. ]
Thanks,
Ingo
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