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Message-ID: <20110501180038.GB27830@elte.hu>
Date: Sun, 1 May 2011 20:00:38 +0200
From: Ingo Molnar <mingo@...e.hu>
To: Andi Kleen <ak@...ux.intel.com>
Cc: Corey Ashford <cjashfor@...ux.vnet.ibm.com>,
Thomas Gleixner <tglx@...utronix.de>,
Pekka Enberg <penberg@...nel.org>,
Vince Weaver <vweaver1@...s.utk.edu>,
torvalds@...ux-foundation.org, linux-kernel@...r.kernel.org,
Peter Zijlstra <peterz@...radead.org>,
Stephane Eranian <eranian@...il.com>,
Carl Love <carll@...ibm.com>
Subject: Re: re-enable Nehalem raw Offcore-Events support
* Andi Kleen <ak@...ux.intel.com> wrote:
> > I would say that most if not all of the events are not generalizable
> > in the sense that you are talking about; the events are very
> > specific to the Torrent chip. For example, the Torrent chip
>
> It's similar also on Intel chips. [...]
You seem to be seriously misinformed about Intel CPUs.
There are a fair number of events on Intel CPUs that can be generalized and
which we have already generalized. Here's a selection:
Performance counter stats for './fill_1b':
2829.562519 task-clock # 0.994 CPUs utilized
27 context-switches # 0.000 M/sec
52 CPU-migrations # 0.000 M/sec
99 page-faults # 0.000 M/sec
8,559,062,611 cycles # 3.025 GHz (20.02%)
2,530,761,381 stalled-cycles-frontend # 29.57% frontend cycles idle (30.03%)
423,070,037 stalled-cycles-backend # 4.94% backend cycles idle (40.04%)
18,043,436,126 instructions # 2.11 insns per cycle
# 0.14 stalled cycles per insn (50.04%)
1,007,704,770 branches # 356.134 M/sec (60.04%)
521,894 branch-misses # 0.05% of all branches (60.02%)
9,424,849 L1-dcache-loads # 3.331 M/sec (50.03%)
1,028,884 L1-dcache-load-misses # 10.92% of all L1-dcache hits (50.02%)
490,266 LLC-loads # 0.173 M/sec (39.99%)
133,226 LLC-load-misses # 0.047 M/sec (10.01%)
2.846836822 seconds time elapsed
Thanks,
Ingo
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