lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Sat, 7 May 2011 22:06:47 +0300
From:	Mike Rapoport <mike.rapoport@...il.com>
To:	Tony Lindgren <tony@...mide.com>
Cc:	Colin Cross <ccross@...gle.com>,
	Stephen Warren <swarren@...dia.com>,
	Linus Walleij <linus.walleij@...ricsson.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Grant Likely <grant.likely@...retlab.ca>,
	Lee Jones <lee.jones@...aro.org>,
	Martin Persson <martin.persson@...ricsson.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	Erik Gilling <konkers@...gle.com>
Subject: Re: [PATCH 1/4] drivers: create a pinmux subsystem

On Wed, May 4, 2011 at 12:22 PM, Tony Lindgren <tony@...mide.com> wrote:
> * Colin Cross <ccross@...gle.com> [110502 14:26]:
>> On Mon, May 2, 2011 at 1:52 PM, Stephen Warren <swarren@...dia.com> wrote:
>>
>> * Drive strength is also controlled through groups of pins, but
>> different groups than pinmux.  Most of the drive strength groups are
>> collections of pad mux groups, but there are a few pins that are in
>> the same pad mux group but a different drive strength group.
>> * Setting a pin as a GPIO overrides its group's mux setting, except
>> for the group's tristate.  You must untristate the entire group to use
>> a single pin as a GPIO.
>> * Each group has a "safe mode", but which mux id to select to enter
>> the safe mode is completely random.
>
> Just posted something in this thread regarding using standard data and
> standard read and write functions, then allow setting platform specific
> custom flags as needed. Care to see if that works for you too?

Tegra does not allow pin muxing on the pin by pin basis. And,
registers that define mux config differ from those that define flags
(pull, driver strength, safe mode etc).

>> In the end, we determined that there was no way to sanely handle
>> setting up Tegra's pinmux programatically, and instead required each
>> board to pass in a table of pinmux settings.
>
> Eventually we should get the package specific table of available pins
> and the board specific settings in devicetree data. And then it's
> easy to set the pins as desired while being able to debug it.
>
> Regards,
>
> Tony
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@...r.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
>



-- 
    Sincerely Yours,
        Mike.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ