linux-kernel - Re: [2.6.39 regression] i915/kms: garbled screen because of 49183b281 (was: Re: Linux 2.6.39-rc7)

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Message-Id: <72a37e$j47ear@orsmga002.jf.intel.com>
Date:	Thu, 12 May 2011 22:41:52 +0100
From:	Chris Wilson <chris@...is-wilson.co.uk>
To:	Melchior FRANZ <melchior.franz@...il.com>,
	linux-kernel@...r.kernel.org
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	dri-devel@...ts.freedesktop.org, Keith Packard <keithp@...thp.com>
Subject: Re: [2.6.39 regression] i915/kms: garbled screen because of 49183b281  (was: Re: Linux 2.6.39-rc7)

On Thu, 12 May 2011 18:49:08 +0200, Melchior FRANZ <melchior.franz@...il.com> wrote:
> * Linus Torvalds -- Tuesday 10 May 2011:
> > But please do test, just to make sure that 39-final is good.
> 
> > Chris Wilson (4):
> >       drm/i915: Only enable the plane after setting the fb base (pre-ILK)
> 
> This patch introduces a bug on my infamous "Acer Travelmate
> 5735Z-452G32Mnss": when KMS takes over, the frame buffer contents
> get completely garbled up on screen, with colored stripes and
> unreadable text (photo on request). Only when X11 is started, the
> screen gets restored again. Closing and re-opening the lid partly
> cures the mess, too: it makes the font readable, though horizontally
> stretched.

So we think that enabling the plane at this point is masking a bug in our
modeset, or that some side-effect of writing those registers or waiting
for that vblank has a vital latching or delay that we have not accounted
for.

Can you please grab intel_reg_dumper from 

  http://cgit.freedesktop.org/xorg/app/intel-gpu-tools

and attach its output after passing nomodeset on your kernel boot
parameters (without starting X). That should capture the registers as they
were left by the BIOS. Alternatively, if you load i915.ko as a module, you
can run intel_reg_dumper before loading the module. Then can you attach
the output from intel_reg_dumper from the VT before starting X (whilst the
display is skewiff) and then after (when the display has recovered). That
may help, unless we are right in that it is in the timing of the register
writes.

Thanks,
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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