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Message-ID: <C10D3FB0CD45994C8A51FEC1227CE22F239E8E4106@shsmsx502.ccr.corp.intel.com>
Date:	Thu, 23 Jun 2011 09:01:19 +0800
From:	"Ma, Ling" <ling.ma@...el.com>
To:	Andi Kleen <andi@...stfloor.org>
CC:	"mingo@...e.hu" <mingo@...e.hu>, "hpa@...or.com" <hpa@...or.com>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH RFC] [x86] Optimize copy-page by reducing impact from HW
 prefetch

Yes, I also have tested 64bit atom, it got 11.6% improvement.
Because older CPU almost all use prefetch-next-line mechanism, the patch should be useful to them.

Thanks
Ling
> -----Original Message-----
> From: Ma, Ling
> Sent: Monday, June 20, 2011 11:43 AM
> To: Ma, Ling; mingo@...e.hu
> Cc: hpa@...or.com; tglx@...utronix.de; linux-kernel@...r.kernel.org
> Subject: RE: [PATCH RFC V2] [x86] Optimize copy-page by reducing impact
> from HW prefetch
> 
> New experiment shows, for 4096 bytes no improvement on snb,
> 10~15% improvement on Core2, 11.6% improvement on 64bit atom.
> 
> Thanks
> Ling

> -----Original Message-----
> From: Andi Kleen [mailto:andi@...stfloor.org]
> Sent: Thursday, June 23, 2011 4:06 AM
> To: Ma, Ling
> Cc: mingo@...e.hu; hpa@...or.com; tglx@...utronix.de; linux-
> kernel@...r.kernel.org
> Subject: Re: [PATCH RFC] [x86] Optimize copy-page by reducing impact
> from HW prefetch
> 
> ling.ma@...el.com writes:
> > impact(DCU prefetcher), and simplify original code.
> > The performance is improved about 15% on core2, 36% on snb
> respectively.
> > (We use our micro-benchmark, and will do further test according to
> your requirment)
> 
> This doesn't make a lot of sense because neither Core-2 nor SNB use the
> code path you patched. They all use the rep ; movs path
> 
> -Andi
> 
> --
> ak@...ux.intel.com -- Speaking for myself only
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