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Message-ID: <alpine.DEB.2.00.1108051608110.4821@router.home>
Date:	Fri, 5 Aug 2011 16:10:48 -0500 (CDT)
From:	Christoph Lameter <cl@...ux.com>
To:	"H. Peter Anvin" <hpa@...or.com>
cc:	Ingo Molnar <mingo@...e.hu>, linux-kernel@...r.kernel.org,
	Andi Kleen <ak@...ux.intel.com>,
	"H. Peter Anvin" <hpa@...ux.intel.com>
Subject: Re: [x86] Fix prefetch instruction



On Fri, 5 Aug 2011, H. Peter Anvin wrote:

> On 08/05/2011 09:18 AM, Christoph Lameter wrote:
> > The prefetchnta instruction used for prefetching on x86 is a special instruction
> > used for streaming that is usually used to avoid polluting the l2 and l3 caches.
> > The cacheline will be evicted rapidly.
> >
> > What we need is a prefetch that puts the cacheline in all levels of the cache hierachy instead.
> > Change the instruction to do that.
> >
> > Acked-by: Andi Kleen <ak@...ux.intel.com>
> > Signed-off-by: Christoph Lameter <cl@...ux.com>
> >
>
> Have you done any performance analysis on this versus the null case?  I
> know there are some workloads where it helps, but if it hurts as many as
> it helps...

No I have not. prefetch IMHO means that the cacheline is fetched early so
that the cacheline is fully available like any other to the code.
prefetchnta does fetch the cacheline too but its not treated like the other cacheline but
preferably thrown out again. Its a "streamfetch" designed for apps that
scan over large amounts of memory and want to avoid cache pollution.

This is surprising to the end user as far as I can tell.

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