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Message-ID: <CAErSpo66U-La7AXCraENWOUvQAuCECRT_eGvJmxC-S4BrN=yAA@mail.gmail.com>
Date:	Fri, 26 Aug 2011 10:21:02 -0600
From:	Bjorn Helgaas <bhelgaas@...gle.com>
To:	Cyrill Gorcunov <gorcunov@...il.com>
Cc:	Suresh Siddha <suresh.b.siddha@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, Ralf Jung <ralfjung-e@....de>,
	Yinghai Lu <yinghai@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] x86, ioapic: Reserve only 128 bytes for IOAPICs

On Fri, Aug 26, 2011 at 12:22 AM, Cyrill Gorcunov <gorcunov@...il.com> wrote:
> On Thu, Aug 25, 2011 at 06:17:06PM -0600, Bjorn Helgaas wrote:
>> On Thu, Aug 25, 2011 at 5:33 PM, Suresh Siddha
>> <suresh.b.siddha@...el.com> wrote:
>> > On Thu, 2011-08-25 at 16:05 -0700, Bjorn Helgaas wrote:
>> >> Previously we reserved 1024 bytes, but that's more space than the IOAPIC
>> >> consumes, and it can cause conflicts with nearby devices.  The known
>> >> requirement is 68 bytes (sizeof(struct io_apic)), and rounding up to a
>> >> power-of-2 gives us 128.
>> >>
>> >
>> > Bjorn, Given the info from Intel that most of its io-apic
>> > implementations has registers up to 0xff offset (reserved), does
>> > reserving just the 128 bytes for the io-apic cause any address conflicts
>> > if the next 128 bytes are allocated (by the OS) for any other device.
>>
>> If the OS allocated the next 128 bytes to another device, it sounds
>> like it would cause a conflict on Intel boxes.  This must be an area
>> that differs between vendors.  I haven't seen a spec that mentions 256
>> bytes as the required minimum MMIO size for IOAPICs, and apparently
>> the AMD IOAPIC decodes 240 bytes or fewer.
>>
>
> Hi Bjorn,
>
> the former idea (as far as I remember) of all this IO_APIC_SLOT_SIZE
> was to be sure the io-apics are allocated with 1K step (which
> is requirements for io-apics), but definitely it doesn't consume
> that much space neither it decode the whole range.
>
> Which means, I would prefer if we have (since we change IO_APIC_SLOT_SIZE
> anyway) some additional check and WARN_ON in this code. Something like
>
>  if (io-apic-base-address & 0x3ff)
>   WARN_ON();
>
> Hm? (also we have bad_ioapic() check, probably should put such test
> there instead).

Is there some spec that requires all IOAPICs to be 1K aligned?  I
don't doubt that's the case; I'd just like to see something more
concrete than folklore.  I'm pretty sure there's some (possibly
secret) "IOAPIC architecture spec," and a section reference to it
would be nice.  Even before my patch, I don't think we actually
checked or enforced any *alignment* -- we only set the size.  I don't
know if it's worth it unless we have a problem it would fix, and it's
conceivable that we'd start warning about a perfectly functional
IOAPIC that's 128-byte aligned.

Bjorn
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