linux-kernel - Re: [PATCH 06/24] C6X: devicetree

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Message-ID: <1315869636.11280.26.camel@deneb.redhat.com>
Date:	Mon, 12 Sep 2011 19:20:35 -0400
From:	Mark Salter <msalter@...hat.com>
To:	Grant Likely <grant.likely@...retlab.ca>
Cc:	linux-kernel@...r.kernel.org, devicetree-discuss@...ts.ozlabs.org
Subject: Re: [PATCH 06/24] C6X: devicetree

On Mon, 2011-09-12 at 14:11 -0600, Grant Likely wrote:
> On Wed, Aug 31, 2011 at 05:26:41PM -0400, Mark Salter wrote:
> > +		interrupt-controller;
> > +		#interrupt-cells = <1>;
> > +		compatible = "ti,c64x+core-pic";
> 
> The interrupt controller isn't addressable?  Is it integrated into
> the CPU?

Yes, that core controller is controlled through registers accessed
with special-purpose instructions, not MMIO. Other controllers, like
megamodule and some as-yet unimplemented use MMIO.

> 
> > +	};
> > +
> > +	soc@...00000 {
> 
> "soc@...0000" to match the 'reg' property of this node.

Okay, I think I need a separate node for that reg property. The SoC
address space does actually start at 0. The registers in that reg
property are "SoC-level" registers holding silicon revision, pin
strap status, etc. All of the SoCs have a "device state config"
node which have registers like that. Instead of having them in the
device state block, this SoC has them in a separate area. I just
got lazy and put them the reg property in the soc node, but I think
it really calls for a separate node.

--Mark

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