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Message-Id: <e39f63$23ptfo@fmsmga002.fm.intel.com>
Date: Tue, 27 Sep 2011 10:01:33 +0100
From: Chris Wilson <chris@...is-wilson.co.uk>
To: Keith Packard <keithp@...thp.com>, Dave Airlie <airlied@...hat.com>
Cc: linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
intel-gfx@...ts.freedesktop.org, Keith Packard <keithp@...thp.com>
Subject: Re: PCH reference clock cleanups
On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard <keithp@...thp.com> wrote:
> Ok, so I'd love to know where in any PCH reference matter someone has
> found a place where the reference clock for any of the PLLs is
> anything other than 120MHz. Can someone find a reference for other frequencies?
Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for
any output other than DP_A. However, the configuration register marks that
as being a test-only mode.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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