linux-kernel - Re: [PATCH v3 00/24] C6X: New architecture

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Message-Id: <201109291233.24623.arnd@arndb.de>
Date:	Thu, 29 Sep 2011 12:33:24 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	Valdis.Kletnieks@...edu
Cc:	Mark Salter <msalter@...hat.com>, linux-kernel@...r.kernel.org,
	linux-arch@...r.kernel.org
Subject: Re: [PATCH v3 00/24] C6X: New architecture

On Wednesday 28 September 2011, Valdis.Kletnieks@...edu wrote:
>   Show Details
>   On Tue, 27 Sep 2011 16:29:41 EDT, Mark Salter said:
> 
> > This architecture supports members of the Texas Instruments family
> > of C6x single and multicore DSPs. The multicore DSPs do not support
> > cache coherancy, so are not suitable for SMP.
> 
> Is there a usage model for the multicore? I know somebody had some patches for
> "HPC dedicated compute cores" that would just basically run a userspace process
> and that's it - would those be applicable here?

No, that's a different thing. Even with dedicated compute cores, you need
cache coherency.

	Arnd
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