linux-kernel - Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio

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Message-ID: <20111024120907.GG6148@opensource.wolfsonmicro.com>
Date:	Mon, 24 Oct 2011 14:09:07 +0200
From:	Mark Brown <broonie@...nsource.wolfsonmicro.com>
To:	Axel Lin <axel.lin@...il.com>
Cc:	linux-kernel@...r.kernel.org,
	Dimitris Papastamos <dp@...nsource.wolfsonmicro.com>,
	Liam Girdwood <lrg@...com>, alsa-devel@...a-project.org
Subject: Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division
 ratio

On Mon, Oct 24, 2011 at 11:32:41AM +0800, Axel Lin wrote:
> According to the datasheet:
> The PLL Output clock division ratio is controlled by BIT[5:4] of
> WM8940_GPIO register(08h).
> Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.

Applied this and patch 2, thanks.
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