linux-kernel - Re: [PATCHv2 RFC] virtio-spec: flexible configuration layout

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Date:	Fri, 11 Nov 2011 13:06:57 +0000
From:	Pawel Moll <pawel.moll@....com>
To:	"Michael S. Tsirkin" <mst@...hat.com>
Cc:	Sasha Levin <levinsasha928@...il.com>,
	Rusty Russell <rusty@...tcorp.com.au>,
	lkml - Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Alexey Kardashevskiy <aik@...abs.ru>,
	Amit Shah <amit.shah@...hat.com>,
	Christian Borntraeger <borntraeger@...ibm.com>,
	Krishna Kumar <krkumar2@...ibm.com>,
	Wang Sheng-Hui <shhuiw@...il.com>,
	"virtualization@...ts.linux-foundation.org" 
	<virtualization@...ts.linux-foundation.org>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
	"avi@...hat.com" <avi@...hat.com>,
	"penberg@...nel.org" <penberg@...nel.org>
Subject: Re: [PATCHv2 RFC] virtio-spec: flexible configuration layout

> > Also, an unrelated questions: With PIO, requests were ordered, which
> > means that if we wrote to the queue selector and then read from a
> > queue register we would read the correct queue info.
> > Is the same thing assured to us with MMIO?
> 
> For real PCI, reads do not bypass writes in PCI. However this
> is only true if both are MMIO or both PIO reads.
> I don't think the ordering of MMIO versus PIO is guaranteed.
> 
> On KVM, the kernel doesn't do anything to guarantee ordering.
> So you get the natural ordering of the CPU.
> 
> > If we write to a queue
> > selector and immediately read from queue info would we be reading the
> > right info, or is there the slight chance that it would get reordered
> > and we would be reading queue info first and writing to the selector
> > later?
> 
> The thing to realize is that write to queue selector with KVM is in the
> end performed by host. And reading queue info means that host will be
> reading the queue selector. So this is a write followed by read
> from the same address. AFAIK no CPUs can reorder such accesses,
> so you get the right info.

(As far as I understand all the complexity ;-) Memory mapped using
ioremap()-like functions should preserve access order. In case of ARM
architecture such memory region is defined (at the page tables level) as
a "device memory" (contrary to "normal memory") and the processor will
not try to be clever about it. I know next-to-nothing about x86, but I
suppose similar idea applies.

Cheers!

Paweł


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