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Message-ID: <CAMbhsRRnKoR3YPWrZzVynVe+dcuU5v0siYvmp2vbBcS1hquC7Q@mail.gmail.com>
Date: Wed, 21 Dec 2011 11:05:41 -0800
From: Colin Cross <ccross@...roid.com>
To: Arjan van de Ven <arjan@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-pm@...ts.linux-foundation.org,
Len Brown <len.brown@...el.com>, Kevin Hilman <khilman@...com>,
Santosh Shilimkar <santosh.shilimkar@...com>,
Amit Kucheria <amit.kucheria@...aro.org>,
Trinabh Gupta <g.trinabh@...il.com>,
Deepthi Dharwar <deepthi@...ux.vnet.ibm.com>,
linux-omap@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: Re: [PATCH 0/3] coupled cpuidle state support
On Wed, Dec 21, 2011 at 4:12 AM, Arjan van de Ven <arjan@...ux.intel.com> wrote:
> On 12/21/2011 10:55 AM, Colin Cross wrote:
>> On Wed, Dec 21, 2011 at 1:44 AM, Arjan van de Ven <arjan@...ux.intel.com> wrote:
>>> On 12/21/2011 10:40 AM, Colin Cross wrote:
>>>
>>>>> this smells fundamentally racey to me; you can get an interrupt one
>>>>> cycle after you think you're done, but before the last guy enters WFI...
>>>>>
>>>>> how do you solve that issue ?
>>>>
>>>> All the cpus have interrupts off when they increment the counter, so
>>>> they cannot receive an interrupt. If an interrupt is pending on one
>>>> of those cpus, it will be handled later when WFI aborts due to the
>>>> pending interrupt.
>>>
>>> ... but this leads to cases where you're aborting before other cpus are
>>> entering..... so your "last guy in" doesn't really work, since while cpu
>>> 0 thinks it's the last guy, cpu 1 is already on the way out/out
>>> already... (heck it might already be going back to sleep if your idle
>>> code can run fast, like in the size of a cache miss)
>>
>> Once a cpu has incremented the counter, it has no way out unless either
>> 1: another cpu (that hasn't incremented the counter yet) receives an
>> interrupt, aborts idle, and clears its idle flag
>> or
>> 2: all cpus enter the ready counter, and call the cpuidle driver's
>> enter function.
>
> .. or it enters WFI, and a physical device sends it an interrupt,
> at which point it exits.
None of the cpus will return to the idle loop until all cpus have
decremented the ready counter back to 0, so they can't wrap around
again.
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