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Message-ID: <80B89753B40C5141A3E2D53FE7A2A8A91968751D@NTXBOIMBX02.micron.com>
Date:	Mon, 16 Jan 2012 19:10:10 +0000
From:	"Sam Bradshaw (sbradshaw)" <sbradshaw@...ron.com>
To:	Jens Axboe <axboe@...nel.dk>, Christoph Hellwig <hch@...radead.org>
CC:	Linus Torvalds <torvalds@...ux-foundation.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"Asai Thambi Samymuthu Pattrayasamy (asamymuthupa) [CONT - Type 2]" 
	<asamymuthupa@...ron.com>
Subject: RE: [GIT PULL] Block drivers for 3.3-rc

> On 2012-01-15 13:44, Christoph Hellwig wrote:
> > On Sun, Jan 15, 2012 at 01:22:05PM +0100, Jens Axboe wrote:
> >> Good point, I had forgotten about the ordered writes, I believe the rest
> >> of the items have been handled. The driver/hw, as it stands, does not
> >> reorder writes and it doesn't have a write back cache. So it should
> >> actually be safe. Any acked write is stable. Sam, correct me if I'm
> >> wrong.
> >
> > I tried to get that out of the micron folks a while ago but don't
> > remember getting an answer.  If that's actually tree please remove
> > the (misnamed) barrier argument from mtip_hw_submit_io, and maybe add
> > a comment that the current hardware can't have a volatile write cache.
> 
> Sure, will do post pull to not mess up the current pull request.
> 
> > Btw, does the hardware claim to have writeback caches in the ATA
> > IDENTIFY words related to it?
> 
> I'll let Sam answer this one and the question above, it's better if it
> comes from the source.

Apologies for not communicating this clearly to the mailing list.  The P320 does not have and will not claim writeback cache support in the IDENTIFY.

We will promptly submit a patch that renames the barrier argument and describes the current state of writeback cache support.

Thanks,
-Sam
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