linux-kernel - Re: [PATCH 2/2] ix86: atomic64 assembly improvements

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Message-Id: <4F17EDE9020000780006D97A@nat28.tlf.novell.com>
Date:	Thu, 19 Jan 2012 09:18:17 +0000
From:	"Jan Beulich" <JBeulich@...e.com>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	<mingo@...e.hu>, "eric.dumazet@...il.com" <eric.dumazet@...il.com>,
	<tglx@...utronix.de>, <luca@...a-barbieri.com>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] ix86: atomic64 assembly improvements

>>> On 18.01.12 at 18:47, "H. Peter Anvin" <hpa@...or.com> wrote:
> On 01/18/2012 08:50 AM, Jan Beulich wrote:
>>>
>>> It's atomic in the same way a MOV is atomic.
>>
>> Then please point me to where this is documented.
>>
>> As I understand it, there is nothing keeping the CPU (or something
>> down the bus) from executing the unlocked version as two 32-bit
>> reads followed by two 32-bit writes.
>>
>>> The CPU could, in fact, execute the locked version at all if the
>>> unlocked version didn't behave like that.
>>
>> Assuming you meant "could not", that's not true: As long as the
>> external world has a way to know that both items are locked (think
>> of the old bus lock mechanism when there were no caches yet),
>> it can very well do so.
>>
>> I do not question that in practice all CPUs behave as described,
>> but without an architectural guarantee (and with the code in
>> question not being used in hot paths afaik) I see no reason why
>> it should depend on undefined behavior.
>>
> 
> Sorry, Jan, if you want to play the documentation lawyer game then there 
> is very little that will get done.  The code is increasingly being used 
> in warm/hot paths and that's actually fair, so I'd like to avoid 
> crapping it up.
> 
> There are, to my knowledge, only three companies which have brought 
> SMP-capable x86 processors to market: Intel, AMD, and VIA and the above 
> holds for them.  A new vendor realistically can't bring a new processor 
> to market which violates a constraint that the existing processor 
> vendors have preserved.
> 
> It is somewhat implied in the SDM section 8.1.1 of volume 3A, but as 
> with many other things it's not written out specifically... I suspect 
> largely because the question hasn't been raised before.

But the code is supposed to be correct even when caches are disabled
(in which case LOCK# will continue to be used even on modern CPUs),
and this case clearly isn't covered by the current implementation. It
may be a good idea to adjust the patch description accordingly, but I
see no reason to change the patch itself.

Jan

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