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Date:	Sun, 29 Jan 2012 17:02:49 +0900
From:	Hitoshi Mitake <h.mitake@...il.com>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	Ingo Molnar <mingo@...e.hu>,
	Matthew Wilcox <matthew.r.wilcox@...el.com>,
	Roland Dreier <roland@...estorage.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	James Bottomley <James.Bottomley@...allels.com>,
	linux-kernel@...r.kernel.org, hpa@...ux.intel.com
Subject: Re: [PATCH] NVMe: Fix compilation on architecturs without readq/writeq

On Tue, Jan 24, 2012 at 01:57, Linus Torvalds
<torvalds@...ux-foundation.org> wrote:
> On Mon, Jan 23, 2012 at 8:05 AM, Hitoshi Mitake <h.mitake@...il.com> wrote:
>>
>> I wrote the patch which adds the new file include/asm-generic/io-nonatomic.h.
>> io-nonatomic.h provides non-atomic version readq()/writeq().
>
> I do wonder if we should do "little-endian" and "big-endian" variations?

Thanks, I'll prepare two variations based on CPU_LITTLE_ENDIAN.

>
> Quoting Willy:
>
>  "For this particular hardware, it's defined to work if you read the
> low order bits first"
>
> so I think we need make that explicit, and make two include files:
>
>   include/asm-generic/io-64b-lo-hi.h
>   include/asm-generic/io-64b-hi-lo.h
>
> or something like that. And thus indirectly document these kinds of
> requirements.
>
> Hmm?
>
>                Linus

I have a question about the order of readl/writel.
If the non-atomic readq/writeq is placed under asm-generic/,
they will be used by every architecture.

I don't know about the minor architectures, but some of them,
like alpha, seems to do reordering of memory access agressively.

Is the reordering is applied to io rw?
Should memory barriers be placed between two readl/writel?

-- 
Hitoshi Mitake
h.mitake@...il.com
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