linux-kernel - Re: [PATCH] Clear previous interrupts after fifo is disabled

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Message-ID: <CAOAMb1CvjxGHSekURXAhw5DL2W2-3Smw3ZTWuAi2E-1UBxHEFg@mail.gmail.com>
Date:	Wed, 29 Feb 2012 11:47:02 +0900
From:	Chanho Min <chanho0207@...il.com>
To:	Russell King - ARM Linux <linux@....linux.org.uk>
Cc:	Alan Cox <alan@...ux.intel.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Shreshtha Kumar Sahu <shreshthakumar.sahu@...ricsson.com>,
	"Kim, Jong-Sung" <neidhard.kim@....com>,
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH] Clear previous interrupts after fifo is disabled

> Which is why my patch explicitly clears the receive interrupt status
> before requesting the interrupt.  Have you read my patch?
This is the hang-up scenario with your patch.

pl011_startup(struct uart_port *port)
 	uap->port.uartclk = clk_get_rate(uap->clk);

	/* Clear pending error and receive interrupts */
	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
	       UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
...
1. RX Interrupt is occurred after interrupt is cleared. Even if
interrupt is masked/disabled before(or probe time), RIS's Rx interrupt
is set to 1. Of course, masked status is zero.
...
2. RXFE of flag register is zero and fifo is not empty before LCRH is cleared.
	writew(0, uap->port.membase + uap->lcrh_rx);
3. RXFE of flag register is changed to '1'  after LCRH is cleared. but
the fifo is not actually empty.
...
4. Finally, We enable interrupts.
	spin_lock_irq(&uap->port.lock);
	uap->im = UART011_RTIM;
	if (!pl011_dma_rx_running(uap))
		uap->im |= UART011_RXIM;
	writew(uap->im, uap->port.membase + UART011_IMSC);
	spin_unlock_irq(&uap->port.lock);
5. The RIS's field which is enabled by IMSC is reflected to MIS as
soon as the interrupt enable. (We checked this on our ARM platform )
6. IRQ context is started. pl011_fifo_to_tty is called by pl011_int.
static int pl011_fifo_to_tty(struct uart_amba_port *uap)
...
	while (max_count--) {
		status = readw(uap->port.membase + UART01x_FR);
		if (status & UART01x_FR_RXFE)
			break;
...
7. pl011_fifo_to_tty can't read any data from DR because of the break
condition for RXFE. Rx interrupt can't be cleared. cpu is looping in
irq context.

This is why we need to be cleared just after LCRH is cleared not
before irq_request. Let's get back to my patch. Even if data is
received before or after interrupt is cleared, flag register will show
actual fifo status. Interrupt handler runs normally after the uart
operation is started up by enabling interrupt.

+       spin_lock_irq(&uap->port.lock);
        writew(0, uap->port.membase + uap->lcrh_rx);
+       /* Clear pending error and receive interrupts */
+       writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
+               UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
+       spin_unlock_irq(&uap->port.lock);

Thanks,
Chanho Min
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