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Message-ID: <CAGS+omAJE_vjdL_H5r6ByJFagOHtH1tDHFwzwWuF2bWxaYdkcw@mail.gmail.com>
Date:	Fri, 13 Apr 2012 19:49:36 +0800
From:	Daniel Kurtz <djkurtz@...omium.org>
To:	Chris Wilson <chris@...is-wilson.co.uk>
Cc:	Daniel Vetter <daniel@...ll.ch>, Keith Packard <keithp@...thp.com>,
	David Airlie <airlied@...ux.ie>,
	dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
	Benson Leung <bleung@...omium.org>,
	Yufeng Shen <miletus@...omium.org>
Subject: Re: [PATCH 4/8 v7] drm/i915/intel_i2c: use WAIT cycle, not STOP

On Thu, Apr 12, 2012 at 4:26 AM, Chris Wilson <chris@...is-wilson.co.uk> wrote:
> On Thu, 12 Apr 2012 02:17:46 +0800, Daniel Kurtz <djkurtz@...omium.org> wrote:
>> On Wed, Apr 11, 2012 at 5:34 AM, Chris Wilson <chris@...is-wilson.co.uk> wrote:
>> > The last major item on the wishlist is solving how to drive the SDVO i2c
>> > over gmbus. I think it is just a matter of massaging in the channel
>> > switch as msg[0].
>>
>> I noticed that random other i2c adapter, but haven't looked at it to
>> know why it is so different than the others.  What is it?
>
> Every command sequence over SDVO is preceded by an instruction to the
> controller as to which function to send the command to. Originally I
> tried to reuse the GPIO method of simply sending that switch command
> immediately followed by the real message, but I never succeeded in
> setting up the SDVO devices in that manner. I suspect what is actually
> required is to rebuild the message to include the preceeding bus switch.
>
> However, if you don't have any SDVO devices to experiment with we can
> find somebody who does.

Sorry, I don't have any SDVO hardware to play with.

> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
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