linux-kernel - Re: [PATCH v2 2/3] ARM: tegra: Add SMMU enabler in AHB

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Message-ID: <20120424.153930.1438573079107186567.hdoyu@nvidia.com>
Date:	Tue, 24 Apr 2012 14:39:30 +0200
From:	Hiroshi Doyu <hdoyu@...dia.com>
To:	"balbi@...com" <balbi@...com>
CC:	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	"ccross@...roid.com" <ccross@...roid.com>,
	"olof@...om.net" <olof@...om.net>,
	"swarren@...dotorg.org" <swarren@...dotorg.org>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"tony@...mide.com" <tony@...mide.com>,
	"hsweeten@...ionengravers.com" <hsweeten@...ionengravers.com>,
	"jamie@...ieiles.com" <jamie@...ieiles.com>,
	"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/3] ARM: tegra: Add SMMU enabler in AHB

From: Felipe Balbi <balbi@...com>
Subject: Re: [PATCH v2 2/3] ARM: tegra: Add SMMU enabler in AHB
Date: Tue, 24 Apr 2012 14:32:52 +0200
Message-ID: <20120424123248.GG8444@...en.pp.htv.fi>

> * PGP Signed by an unknown key
> 
> Hi,
> 
> On Tue, Apr 24, 2012 at 03:05:15PM +0300, Hiroshi DOYU wrote:
> > @@ -95,6 +98,21 @@ static inline void gizmo_writel(unsigned long value, unsigned long offset)
> >  	writel(value, tegra_ahb->regs + offset);
> >  }
> >  
> > +#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> > +
> > +void tegra_ahb_enable_smmu(void)
> > +{
> > +	unsigned long val;
> > +
> > +	val = gizmo_readl(AHB_ARBITRATION_XBAR_CTRL);
> > +	val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE_DONE <<
> > +		AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE_SHIFT;
> > +	gizmo_writel(val, AHB_ARBITRATION_XBAR_CTRL);
> > +}
> > +EXPORT_SYMBOL(tegra_ahb_enable_smmu);
> 
> ok, so this is the only place where you need that global pointer. Who
> would call this ? Can you do runtime detection of the SoC and enable
> SMMU based on that ?
> 
> I mean, will this function always be called for TEGRA 3 SoCs or is there
> another condition to that ?

Only Tegra3 has SMMU.
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