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Message-ID: <DB904C5425BA6F4E8424B3B51A1414D16F64F8527E@NWD2CMBX1.ad.analog.com>
Date: Thu, 17 May 2012 22:41:21 -0400
From: "Zhang, Sonic" <Sonic.Zhang@...log.com>
To: Shubhrajyoti Datta <omaplinuxkernel@...il.com>
CC: Ben Dooks <ben-linux@...ff.org>,
Wolfram Sang <w.sang@...gutronix.de>,
"linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>,
"uclinux-dist-devel@...ckfin.uclinux.org"
<uclinux-dist-devel@...ckfin.uclinux.org>
Subject: RE: [PATCH 4/8] i2c: i2c-bfin-twi: Tighten condition when failing
I2C transfer if MEN bit is reset unexpectedly.
>-----Original Message-----
>From: Shubhrajyoti Datta [mailto:omaplinuxkernel@...il.com]
>Sent: Thursday, May 17, 2012 7:31 PM
>To: Zhang, Sonic
>Cc: Ben Dooks; Wolfram Sang; linux-i2c@...r.kernel.org; LKML; uclinux-dist-
>devel@...ckfin.uclinux.org
>Subject: Re: [PATCH 4/8] i2c: i2c-bfin-twi: Tighten condition when failing I2C
>transfer if MEN bit is reset unexpectedly.
>
>On Wed, May 16, 2012 at 12:50 PM, <sonic.zhang@...log.com> wrote:
>> From: Sonic Zhang <sonic.zhang@...log.com>
>>
>> Correct I2C transfer may fail because interrupt status bits XMTSERV and
>> RCVSERV are not checked when MCOMP interrupt is handled.
>>
>Could you expand MCOMP?
Master transfer complete (MCOMP)
[1] The initiated master transfer has completed. In the absence of a
repeat start, the bus has been released.
[0] The completion of a transfer has not been detected.
Regards,
Sonic
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