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Message-ID: <CAM=Q2ctYVmok6bJu4kRWM2CX07vp7NS0VTHyeVzbJa3TttLU2Q@mail.gmail.com>
Date: Fri, 18 May 2012 11:52:41 +0530
From: Shubhrajyoti Datta <omaplinuxkernel@...il.com>
To: "Zhang, Sonic" <Sonic.Zhang@...log.com>
Cc: Ben Dooks <ben-linux@...ff.org>,
Wolfram Sang <w.sang@...gutronix.de>,
"linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>,
"uclinux-dist-devel@...ckfin.uclinux.org"
<uclinux-dist-devel@...ckfin.uclinux.org>
Subject: Re: [PATCH 4/8] i2c: i2c-bfin-twi: Tighten condition when failing I2C
transfer if MEN bit is reset unexpectedly.
On Fri, May 18, 2012 at 8:11 AM, Zhang, Sonic <Sonic.Zhang@...log.com> wrote:
>
>
>>-----Original Message-----
>>From: Shubhrajyoti Datta [mailto:omaplinuxkernel@...il.com]
>>Sent: Thursday, May 17, 2012 7:31 PM
>>To: Zhang, Sonic
>>Cc: Ben Dooks; Wolfram Sang; linux-i2c@...r.kernel.org; LKML; uclinux-dist-
>>devel@...ckfin.uclinux.org
>>Subject: Re: [PATCH 4/8] i2c: i2c-bfin-twi: Tighten condition when failing I2C
>>transfer if MEN bit is reset unexpectedly.
>>
>>On Wed, May 16, 2012 at 12:50 PM, <sonic.zhang@...log.com> wrote:
>>> From: Sonic Zhang <sonic.zhang@...log.com>
>>>
>>> Correct I2C transfer may fail because interrupt status bits XMTSERV and
>>> RCVSERV are not checked when MCOMP interrupt is handled.
>>>
>>Could you expand MCOMP?
>
> Master transfer complete (MCOMP)
> [1] The initiated master transfer has completed. In the absence of a
> repeat start, the bus has been released.
> [0] The completion of a transfer has not been detected.
>
A trivial suggestion may be the changelog could be enhanced.
Thanks for the explanation.
>
> Regards,
>
> Sonic
>
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